1. Field of the Invention
The present invention relates generally to interface circuits for non-superimposed two-phase timing signal generators, having a pulse waveform of rectangular type and, more particularly, to an interface circuit, using insulated-gate field-effect transistors of the MOS (Metal Oxide Semiconductor) type, designed to suppress the noise caused by fluctuations of the supply voltage in these timing signals and to supply, in this way, low-noise timing signals. The low-noise timing signals can be used to drive the circuits of devices in which low sensitivity to supply voltage variations is an important factor.
2. Discussion of the Related Art
The effect which supply voltage variations have on the output of the circuit being supplied, generally known in the prior art as "power-supply rejection ratio" (PSRR) has become an increasingly important design parameter, particularly in the case of recent circuit structures in which analog and digital sub-systems are used together in an integrated circuit.
In this case it is, in practice, almost impossible to prevent the noise caused in one sub-system by supply voltage variations from introducing noise into the other sub-system.
In this respect, it will be noted, for example, that supply voltage variations deriving from causes inside or outside of the integrated circuit itself, are directly transferred to the digital timing signals supplied by generators supplied with this voltage.
These signals are generally obtained by a simple short-circuiting of the generator circuit output, for specific time intervals, alternately at the positive and the negative terminal of the supply.
The peak-to-peak amplitude of the timing signals is therefore equal to that of the entire supply voltage, which may lead to variations if no suppression is carried out.
The "noise" of the supply source is then transferred, via these digital timing signals, to the digital or analog sub-systems to which they are supplied, thereby impairing the efficiency of the entire system. This problem must also be taken into account in the construction of switched capacitor circuits (SCC), based on elementary circuit structures comprising one capacitor and two or more switches formed by metal-oxide-semiconductor (MOS) field-effect transistors. One plate of the capacitor is alternately brought to two separate reference potentials, which are opposite to one another with respect to a fixed potential at which the other plate is maintained, by means of switches which are controlled by non-superimposed two-phase timing signals having a pulse waveform of rectangular type.
As is known to persons skilled in the art, these elementary switched capacitor circuit structures are equivalent, as regards their electrical behavior, to a resistance and are particularly suitable for use in the construction of high quality integrated circuit active filters used in transmission systems of PCM (Pulse-Code-Modulation) type.
The use of an equivalent switched capacitor circuit in place of a conventional resistor provides considerable advantages in terms of accurate construction and compact integration and is, moreover, fully compatible with the technologies used for digital integrated circuits.
The use of switched capacitor circuits in monolithically integrated active filters is not only economically advantageous, but also enables these filters to be provided with characteristics which may be better controlled, without the need for subsequent operational calibration.
The advantages set out above would, however, be completely cancelled out if the noise caused by supply voltage variations were transferred to the filter output, by the synchronizing signals for controlling the MOS transistor switches.
The way in which this can happen is shown below with reference to FIG. 1 which takes as its example the known circuit diagram of a switched capacitor differential integrator circuit used as a basic component in the active filters of PCM transmission systems.
The circuit diagram of FIG. 1 shows a capacitor C.sub.s, two pairs of MOS field-effect transistors, M11, M12 and M21, M22, and an operational amplifier AL of differential type.
The transistors, all of N-channel or P-channel type, act as switches for switching of the capacitor C.sub.s. The gate electrode of the transistor M11 and the gate electrode of the transistor M21 are coupled to a first input terminal C.
The gate electrode of the transistor M12 and the gate electrode of the transistor M22 are coupled to a second input terminal C.
The two input terminals C and C are coupled to the output terminal of a non-superimposed two-phase timing signal generator having a pulse waveform of rectangular type (not shown).
A first terminal of the capacitor C.sub.s is coupled to the earth of the circuit via the transistor M11 and to the inverting input (-) of the amplifier A1 via the transistor M12.
The second terminal of the capacitor C.sub.s is coupled to a first and a second voltage signal input V.sub.1 (t) and V.sub.2 (t) via the transistor M21 and the transistor M22 respectively. The non-inverting input (+) of the amplifier A1 is coupled to earth. The voltage signal output V.sub.o (t) of the amplifier A1 is coupled, via an integration capacitor CI, to the inverting terminal (-) at a connection point S which acts as a summing node.
It can immediately be seen that when a high signal level is supplied to the gate electrode of the transistor M12 and thus the charge stored in the capacitor C.sub.s is injected, via the transistor M12, if it is of the N-channel type, into the summing node, the possible noise with which the timing signal itself is affected as a result of voltage variations in the supply source of its generator, is transferred to this node via the gate channel stray capacitance C.sub.GS of the transistor M12.
The output signal of the operational amplifier A1 is also impaired as a result of this noise.
A variation .delta.V.sub.C of the voltage level of the timing signal supplied to the transistor M12 also causes a variation .delta.V.sub.o of the level of the output signal v.sub.o (t) expressed by the relationship: ##EQU1## The output signal of a more complex circuit system, for example of an active filter in its entirety, comprising various switched capacitor circuit structures of the above type, is further impaired as a result of the numerous connections which exist, via the timing signals, between the summing nodes at the input of the operational amplifiers and the supply source or sources.
The main paths for these connections are formed by the stray capacitances of the monolithically integrated capacitors, by the stray capacitances of the MOS transistors which act as switches and by the stray capacitances of the connection tracks.
In order to remedy this drawback, solutions mainly of a technological type are known, such as, for example, shielding both the integrated capacitors and the connection tracks with diffusion regions connected to earth and biasing the diffusing regions in which the MOS transistors are provided by stabilized voltages.
In addition, in order to limit the effect of the transconductance between the channel and the substrate in MOS transistors for input to the operational amplifiers, generally comprising N-channel transistors, the source region of each of these transistors may be coupled to the substrate.
A further known solution of the problem of the noise sensitivity to supply sources, used specifically for active filters with high selectivity and operating exclusively at a circuit level, involves the use of the circuit system in a completely differential manner in order to cancel the effect of the noise in the output signal. This solution leads, however, to design restrictions and higher costs for integrated circuit uses.